This invention relates in general to apparatus and method for data communication and, more particularly, to serial data path architecture for use with a very large scale integration semiconductor circuit.
Communication systems using parallel address and parallel data bus interconnection architecture for transferring data among memory locations, input/output (I/O) registers, processing elements and other functional units are well known. For typical VLSI semiconductor circuits these parallel interconnections among various functional units may occupy a large portion of available usable masking area which area may be more beneficially allocated for additional functional units and circuitry. Alternatively, reduction of the area required for address/data bus interconnection circuitry will enable the overall VLSI semiconductor circuit (typically referred to as a chip) size to be reduced. Further, usurpation of available masking area by address/data bus parallel interconnection circuitry among functional units increases as both bit width of data and address size increase.
Benefits realizable by reducing circuit size include increasing the yield of acceptable chips from a wafer and obtaining more chips from a given size wafer during manufacture. The increased yield is generally obtainable since the ratio of acceptable chips to the total number of chips produced from a wafer is inversely proportional to a function of the area of each chip. By obtaining more chips per wafer, the manufacturing cost per chip is reduced since the cost to process a wafer and form chips therefrom is relatively fixed.
It would therefore be desirable in the art of integrated circuitry to provide means and method for serial data transfer between the various functional units of a VLSI semiconductor chip.
Accordingly, it is an object of the present invention to provide serial data/address interconnection circuitry on a VLSI chip.
Another object of the present invention is to increase the number of functional units which can be placed on a semiconductor chip.
A further object of the present invention is to reduce the area of VLSI circuitry required for data/address interconnection circuitry among functional units on a VLSI semiconductor chip.
Still another object is to reduce the overall size of a semiconductor chip.